A few weeks ago, ARM announced a new core, a reengineered version of its Coretex M0 that ARM calls the M0+. The M0+ core is binary compatible with the original M0, but it was developed from scratch rather than by editing the original design.
The core takes aim at power-critical designs that would normally use 8- or 16-bit MCUs. One feature that should particularly appeal to 8-bit developers is single-cycle access to I/O and other critical peripherals. Another useful feature is a linear 4GB address space to eliminate the need for paging and other software complications.
Freescale, a lead partner with ARM during the core's development, is first out the gate with the announcement of an M0+ MCU, the Kinetis L-series, with full details due out in June. The MCU will also be showing at this week's Design West show in San Jose, Calif.
ARM's new core has also been licensed by NXP. The company expects that products it develops on the M0+ core will continue the trend toward replacing 8-bit applications with 32-bit devices that NXP has seen with adoption of its M0-based MCUs.
Although the case has been made that 8-bit devices still have a long market lifetime ahead of them, it won't be because 32-bit vendors have yielded the application space where 8-bits thrive. All the companies working with the M0+ are seeking to wrestle those applications away by chipping away at the few advantages remaining to 8-bit devices. With the implementation of 8-bit-like behaviors in the M0+, for instance, vendors are also working to reduce software development complexity down to 8-bit levels with new, simpler tools.
How successful that effort will be remains to be seen. Inertia still seems to play a significant role in MCU choice, showing itself as a bias favoring the familiar architecture over the potentially more powerful new one. It will take time as well as compelling advantages to shift developer thinking. And not all will be convinced.
These 32-bit devices seek to invade 8-bit territory, but I expect that it will be an uphill battle.
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