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Aubrey Kagan

First Steps With Programmable System on Chip

Aubrey Kagan
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antedeluvian
antedeluvian
12/1/2012 10:15:34 AM
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Re: Why a shift register
vish

I am not quite sure of your question. My discussion with Rich evolved around the DMA on the from the 12 bit SAR ADCs. If you are prepared to work with the internal configurable logic on the PSoC you can achieve pretty much anything you can imagine using logic.

If you are referring the the CPU access of the 12 bit SAR ADCs, then the API allows you to read 8, 10 or 12 bits depending on your fucntion call. Obviously the 8 bit read will return all 8 MSBs as a byte. The other two read types return a 16 bit number with the MSBs equal to zero.

The 12 bit SAR ADCs are only on the PSOC5 (ARM core).

The PSoC3 (8051 core) and PSoC5 also have the option to additionally configure several Delta Sigma ADCs, with a much greater resolution. I am at home so I can't verify this easily, but I believe they are configurable up to 20 bits and perhaps higher. Of course they are much slower than the SAR ADCs. The SAR ADCs cannot have the number of bits changed, the software merely returns the chosen number of bits read. The Delta-Sigmas on the other hand, can be adjusted for number of bits, although I imagine the read functions will operate similarily. I have not worked with the Delta Sigmas yet.

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vish2207
vish2207
12/1/2012 2:18:28 AM
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Re: Why a shift register
@AD, we some times come to similar situation. There is 12 bits of result which is stored in two 8 bit registers. We align the A/D result to the right align so that among 2 registers of 8 bits, most significant 8 bits register contains upper 4 bits of result and least significant 8 bits register contains remaining 8 bits of A/D result. We simply pad the upper most 4 bits with 0. Is it possible in PSoC?

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Rich Quinnell
Rich Quinnell
11/29/2012 3:13:18 PM
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Re: Why a shift register
Ah, I see. So those connections are relatively fixed and are not configurable. Too bad. But I guess it might be too confusing if they were. Your shift register approach sounds like a good workaround.

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Rich Quinnell
Rich Quinnell
11/29/2012 1:18:59 PM
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Helpful link, maybe
AD, found this link on EETimes that I thought might be of use to you. Of course, it may be a bit late now that you're elbow deep into the thing....

Seven steps to embedded designs made easier with PSoC Creator

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antedeluvian
antedeluvian
11/28/2012 8:22:07 PM
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Re: Why a shift register
do you need that shift register setup? Couldn't you just configure the thing to DMA only the eight MSB of the ADC output to the UART, and simply not connect the rest?


The A/D can be set to operate at 8, 10 or 12 bits, but that is only for the different read functions. It always does a 12 bit conversion, so 8 bit configuration was no help. Although the DMA can access 1, 2, or 4 bytes (if I remember correctly) I seem to remember trying to transfer 8 bits  and not succeeding. It seemed to me that the DMA access depends on the internal access network. SOme things are 8 bits and others are 16 and you can't access the 16 as an individual byte.

At any rate since the data conversion is always 12 bits, the most significant 8 bits would cross the byte boundary and so you would need to access both bytes.

So at this juncture my answer is no, but all the registers etc are built of smaller blocks. With greater knowledge it may be possible to achieve this. I will try to keep this question in mind as I work through the project.

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Rich Quinnell
Rich Quinnell
11/28/2012 7:55:58 PM
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Why a shift register
AD, do you need that shift register setup? Couldn't you just configure the thing to DMA only the eight MSB of the ADC output to the UART, and simply not connect the rest?

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